1. Field of the Invention
The present invention relates to a memory device and fabricating method thereof, and more particularly, to a mono-gate memory device and fabricating method thereof, in which a mono split-gate is provided by forming an ONO (oxide-nitride-oxide) layer prior to a logic circuit process and forming polysilicon on the ONO layer and the like.
2. Discussion of the Related Art
Generally, semiconductor devices are categorized into a volatile memory and a non-volatile memory. RAMs such as DRAM (dynamic random access memory), SRAM (static random access memory), and the like belong to the volatile memory category, which enables data input and storage with power application thereto only, but fails to keep storing data therein since the stored data is lost in case of power removal.
In a fabricating process, the non-volatile memory devices are categorized into (i) a floating gate type and (ii) an MIS (metal insulator semiconductor) type having a multi-layer (dual or triple layer) of at least two kinds of dielectric materials.
The floating gate type memory device implements memory characteristics using a potential well, and mainly employs an ETOX (EPROM tunnel oxide) structure applicable to flash EEPROM (electrically erasable programmable read only memory).
On the other hand, the MIS type memory device performs a memory function using charge traps in a dielectric bulk, at a dielectric-to-dielectric interface, and/or at a dielectric-to-semiconductor interface, and mainly employs a MONOS/SONOS (metal or silicon/oxide-nitride-oxide [ONO]/semiconductor) structure, which is also applicable to flash EEPROM.
FIG. 1 is a cross-sectional diagram of a conventional SONOS type memory device. Referring to FIG. 1, the SONOS type memory device includes a tunnel oxide layer 101, a trap nitride layer 102, a block oxide layer 103, and a gate 104, stacked in turn on a P type silicon substrate 100 provided with a source 105 and drain 106.
The SONOS type memory device in FIG. 1 is a charge-trap type device using a mechanism in which an electric charge tunnels through oxide film 101 on silicon 100 by a voltage applied to gate 104, causing electric charges to be injected into or to be released from a trap within silicon nitride layer 102 or at its interface with oxide film 101. In this case, a thin ONO layer is used instead of polysilicon to decrease the overall thickness of the memory device, relative to the floating gate type device. Moreover, using a tunnel oxide layer below several nanometers, it is able to remarkably reduce a size of a memory cell. Hence, SONOS type memory devices enable a high degree of integration, as well as a remarkably lowered drive voltage.
However, in case of the conventional SONOS memory device, leakage current generated from a non-selected memory cell is regarded as flowing from a selected memory cell. For instance, an over-erase phenomenon appears to lead the selected memory cell to be misread as erased on programming. Hence, the SONOS cell design or configuration may affect the logic circuit characteristics of the memory device.